1. Field of the Invention
The present invention relates to computing coprocessor architectures and more specifically relates to methods for saving and restoring context in I/O coprocessors utilizing scatter/gather lists for manipulating blocks of memory.
2. Discussion of Related Art
It is common in computing and electronic applications for a processor device to manipulate large blocks of memory for particular application purposes. For example, DMACs are often used in conjunction with general-purpose processors (xe2x80x9cCPUxe2x80x9d) to handle movement of large blocks of data with minimal overhead processing by the general-purpose CPU. The DMAC is programmed by the CPU to indicate the block of memory to be manipulated including, for example, a source location, destination location, and count of the number of units of memory to be moved. The DMA controller then performs the requested block memory move operation without further intervention by the CPU. This generally frees the CPU computational power for processing of other operations for the particular application. When the DMA controller completes the block memory operation, it notifies the CPU of the completion and the CPU then continues processing as necessary following completion of the block memory operation.
It is also common for intelligent IOP devices to include similar block memory manipulation structures. For example, a SCSI bus controller or Fibre Channel controller may include programmable capabilities such that it directly manipulates blocks of memory to transfer information between the SCSI bus (or Fibre Channel medium) and the system memory of a host computer. Similar to the purpose of a DMAC, IOPs serve to offload the general-purpose CPU from the lower-level responsibilities of manipulating individual units of memory in the block memory operations. Rather, the DMAC or IOP is programmed to perform the particular block operation and interrupt or otherwise notify the general-purpose CPU when the block operation is completed.
It is common in the present day DMACs and IOPs to include a capability for processing multiple block memory operations under the programmable direction of an associated general-purpose CPU. Specifically, the general-purpose CPU may supply information to the DMAC or IOP to signify a plurality of memory blocks to be used in a plurality of block transfer operations. Frequently, a list of memory blocks to be manipulated is supplied to the DMAC or IOP by the general-purpose CPU. The list is often referred to as a scatter/gather list (xe2x80x9cSGLxe2x80x9d). The list may, for example, identify a plurality of blocks of memory to be xe2x80x9cwrittenxe2x80x9d to one or more destination locations or may specify the xe2x80x9creadingxe2x80x9d of noncontiguous source locations of memory for transfer to one or more destination locations (i.e., the xe2x80x9cscatteringxe2x80x9d or xe2x80x9cgatheringxe2x80x9d of memory blocks).
The scatter/gather list may be specified utilizing any of a variety of well-known computing data structures to define a list of such elements for processing within the DMAC or IOP.
DMACs and IOPs that process scatter/gather lists generally embed significant processing power to perform their respective I/O processing functions and to process the scatter/gather lists. Such intelligent coprocessors (i.e., DMACs and IOPs) have programmed instructions operating within to perform the designated I/O operations and to process the scatter/gather lists. Processing of the scatter/gathers lists generally involves memory manipulations to fetch entries from the scatter/gather list and starting the block transfer operation defined by the fetched scatter/gather list entry. This processing is typically coded as xe2x80x9cfirmwarexe2x80x9d within the intelligent coprocessor.
As demands for additional I/O processing features within intelligent coprocessors increase to further offload processing within the general-purpose processor, processing requirements within the intelligent coprocessors similarly increases. In other words, the processing load is shifted from the general-purpose processor to the intelligent coprocessor. Processing capability within such intelligent coprocessor devices is becoming a valuable resource to be carefully allocated. Within present DMACs and IOPs, significant processing capabilities are now allocated to firmware for processing of scatter/gather list entries. In particular, scatter/gather list processing entails the fetching of scatter/gather list elements, parsing out of data values from each such fetched scatter/gather list elements, and following list data structure information to locate a next scatter/gather list element.
Further, processing of the block transfer operation defined by each individual scatter/gather list element may require a sequence of intermediate steps so that multiple block transfers may be processed in parallel within the DMAC or IOP. In other words, processing of one scatter/gather list element may be temporarily suspended while other block transfer operations defined by other scatter/gather list elements continue forward. Saving and restoring context information when such block transfer operations are paused and resumed can consume significant processing power of the intelligent coprocessor. Present techniques require that the IOP code (xe2x80x9cfirmwarexe2x80x9d) expend significant processing power to traverse the scatter/gather list to locate and save needed context where the block transfer operations were paused and then to restore the scatter/gather list processing when the block transfer operation is to be resumed.
It is evident from the above discussion that a need exists for an improved architecture providing a standardized architecture and method for processing scatter/gather list within intelligent coprocessors. In particular a need exists to improve the processing of scatter/gather list processing where block transfers are paused and resumed.
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing structure and associated methods for a standardized data path engine including scatter/gather list processing capabilities and for the saving and restoring of context information relating to scatter/gather list processing in using such a standardized data path engine. Specifically, the present invention defines a scatter/gather list circuit architecture and method of operation for integration within intelligent coprocessors. Still more specifically, the present invention provides a circuit architecture and associated methods for a standardized scatter/gather list processor element to be incorporated within intelligent coprocessors. The standardized architecture includes a register interface for both inbound and outbound transfer operations in the preferred embodiment to simplify context save and restore capabilities to pause a block transfer operation prior to completion.
A first aspect of the present invention provides for a method operable in an intelligent coprocessor having a scatter/gather list processor where the method comprises the steps of: pausing processing of a scatter/gather list by the scatter/gather list processor; reading current context regarding progress of processing of the scatter/gather list by the scatter/gather list processor, wherein the current context comprises values read from registers in the scatter/gather list processor; writing the current context to the registers to restore the current context in the scatter/gather list processor; and resuming processing of the scatter/gather list by the scatter/gather list processor.
A further aspect of the present invention provides for modifying the current context prior to writing where the modification is responsive to a Modify Data Pointers message.
Still another aspect of the present invention provides a scatter/gather list processor circuit for processing of a scatter/gather list within an intelligent coprocessor comprising: a current context memory containing information regarding processing of a scatter/gather element of the scatter/gather list wherein the current context memory provides a read/write interface to other elements of the intelligent coprocessor; and a control element coupled to the current context memory for processing of the scatter/gather list to perform block transfer operations defined by scatter/gather elements of the scatter/gather list.
Yet another aspect provides that the current context memory comprises a plurality of registers.